Strain engineering is utilized to evaluate the strain within the transistor channel in order to optimize the semiconductor device performance. Strain modulation either enhances electron or hole mobility within the transistor channel and thereby enhances conductivity of the transistor channel.
Strain engineering applications in Complementary Metal Oxide Semiconductor (CMOS) transistors varies depending upon whether the implementation is on a Positive channel Metal Oxide Semiconductor (PMOS) transistor or a Negative channel Metal Oxide Semiconductor (NMOS) transistor. The PMOS and NMOS transistors respond differently to different forms of strain. The conductivity of a PMOS channel improves when applied with compressive strain upon the channel, whereas the conductivity of a NMOS channel improves when applied with tensile strain upon the channel. Conversely, the conductivity of PMOS channel worsens when applied with tensile strain upon the channel, whereas the conductivity of NMOS channel worsens when applied with compressive strain upon the channel.
Strain engineering techniques have become an important factor to achieve optimum performance of the semiconductor devices. Strain engineering techniques impact numerous parameters, including speed and leakage of electrical current across the transistor channel.
An example of the continuous advances in semiconductor process is the decrease of feature size, e.g., the decrease of transistor channel width, within the semiconductor process. Hence, small variations in semiconductor processes that previously had insignificant impacts on large features, now contribute a significant impact, e.g., increase of leakage under a gate of the transistor. Furthermore, higher performance devices require tighter process control and variations.
A problem that occasionally happens in strain engineering is an imbalance of strain-inducing composites. The imbalance occurs due to a micro-loading effect, in which concentrations of the strain-inducing composites to be deposited varies significantly between different regions during the growth process. Such an imbalance of growth between regions results in varied performance of the transistors of the different regions.
It is within this context that the embodiments described herein arise.